This invention relates to cancellation of line reflections in a clock distribution network, and more particularly, to cancellation of such reflections in such a way that the reflections are not accidentally misinterpreted as events. Conventional clock distribution networks are arranged in a manner known as "daisy-chaining" as shown in FIG. 1. In FIG. 1, a source 10 of a clock signal is applied through a line damping resistor 40 to a network which in the configuration shown, for the sake of simplicity, has two devices, a first device 20 and a second device 30. The system also includes a termination 50 modeled as a resistor 60 and a capacitor 70.
In systems such as that shown in FIG. 1, a clock signal originating from the clock signal source 10 propagates to the first device 20 and then to the second device 30. Upon encountering the second device 30, however, at least part of the energy of the clock pulse will be reflected back toward the first device 20. This can result in a secondary pulse appearing at the clock input of the first device 20, which can cause double clocking within one clock cycle, and which can in turn result in operating errors such as misregistration of data flow.